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xr
DEC 2006
Preliminary
XRT91L31
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION
The XRT91L31 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The internal CDR unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. Either the internally recovered clock or the externally recovered clock can be used for loop timing applications. The chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide LVTTL system interface in both receive and transmit directions. The transmit section includes an option to accept a FIGURE 1. BLOCK DIAGRAM OF XRT91L31
parallel clock signal from the framer/mapper to synchronize the transmit section timing. The device can internally monitor Loss of Signal (LOS) condition and automatically mute received data upon LOS. An on-chip SONET/SDH frame byte and boundary detector and frame pulse generator offers the ability recover SONET/SDH framing and to byte align the receive serial data stream into the 8-bit parallel bus. APPLICATIONS
* SONET/SDH-based Transmission Systems * Add/Drop Multiplexers * Cross Connect Equipment * ATM and Multi-Service Switches, Routers and
Switch/Routers
* DSLAMS * SONET/SDH Test Equipment * DWDM Termination Equipment
STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER
TXDI[7:0]
8
TXPCLK_IO REFCLKP/N TTLREFCLK
PISO (Parallel Input Serial Output)
ENB
Re-Timer
TXOP/N
MUX Div by 8
ENB
XOR
CMU DLOOP
RLOOPS
ALOOP
MUX
CDRAUXREFCLK
MUX
RXDO[7:0]
SIPO (Serial Input Parallel Output)
CDR MUX
RXIP/N
8
XRXCLKIP/N RXPCLKO Div by 8
Loop Filters
Control Block
Clock Control
CAP1N
CAP2N
CAP1P
CAP2P
DLOSDIS
LOSEXT
OOF FRAMEPULSE
CDRDIS
CMUFREQSEL
LOOPTIME
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
STS-12/STS-3
CDRREFSEL
PIO_CTRL
RLOOPS
DLOOP ALOOP
Reset
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES
xr
REV. 1.0.2
* Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications * Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1
155.52 Mbps
* Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
* Ability to disable and bypass onchip CDR for external based received reference clock recovery thru
Differential LVPECL input pins XRXCLKIP/N
* 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1
mode of operation
* Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz or
77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations
* Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation * Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus * Diagnostics features include LOS monitoring and automatic received data mute upon LOS * Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode * Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing
signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the transceiver transmit timing.
* Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, Bellcore TR-NWT-000253 and GR-253-CORE, GR-253 ILR SONET Jitter specifications.
* Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B
LVTTL and LVCMOS standard.
* Operates at 3.3V with 3.3V I/O * Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode Typical Power Dissipation * Package: 10 x 10 x 2.0 mm 64-pin QFP
2
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REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)
AVDD PIO_CTRL GND VDD3.3 RRCLK_1 GND RRPOS_1 GND RRNEG_1 AGND_RX RCLKES AVDD3.3_RX NC CAP2P VDD CAP2N DS3/E3_2 CAP1N SDO CAP1P FSS AVDD3.3_TX RRNEG_2 AGND_TX RRPOS_2 TTLREFCLK RRCLK_2 GND GND VDD3.3 AVDD LOSEXT 49 50 49 51 50 52 51 53 52 54 53 55 54 56 55 57 56 58 57 59 58 60 59 60 61 61 62 62 63 63 64 64 48 48 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 3132 3031 2930 2829 2728 2627 2526 2425 2324 2223 2122 2021 1920 1819 1718 17
PART NUMBER XRT91L31IQ
RESET RESET LOOPTM_NOJA LOOPTIME CMUFREQSEL CMUFREQSEL VDD_PECL VDD_PECL TXOP TXOP TXON TXON LOSDDIS DLOSDIS EXTRXCLKIP XRXCLKIP EXTRXCLKIN XRXCLKIN VDD_PECL VDD_PECL OOF OOF CDRDIS CDRDIS RXIP RXIP RXIN RXIN VDD3.3 VDD/CDR_BW REFCLKP REFCLKP
1 12 23 34 45 56 67 78 89 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16
AGND TXPCLK_IO FL1 TXDI7 STS1_1 TXDI6 MCLK_1 GND GND TXDI5 RCLK_1 TXDI4 RPOS_1 TXDI3 RNEG_1 TXDI2 VDD TXDI1 RNEG_0 TXDI0 RPOS_0 STS12/STS3 RCLK_0 CDRREFSEL GND VDD3.3 MCLK_0 DLOOP DJA_1/SDI RLOOPS AGND ALOOP
XRT91L30 XRT91L31
AGND FL_2 CDRAUXREFCLK STS1_2 VDD3.3 DJA_2/CS FRAMEPULSE MCLK_2 RXPCLKO GND GND RXDO7 RCLK_2 RXDO6 VDD RXDO5 RNEG_2 RXDO4 RPOS_2 RXDO3 GND RXDO2 DJA_0/SCLK GND DS3/E3_0 RXDO1 STS1_0 RXDO0 FL0 VDD3.3 AGND REFCLKN
ORDERING INFORMATION
PACKAGE 64 Pin Lead QFP OPERATING TEMPERATURE RANGE -40C to +85C
3
XRT91L31
REV. 1.0.2
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L31 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2 FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)............................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3 TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS ..........................................................................................................4
.....................................................................................................................................................................4 HARDWARE CONTROL ....................................................................................................................................4 TRANSMITTER SECTION ..................................................................................................................................7 RECEIVER SECTION........................................................................................................................................9 POWER AND GROUND ..................................................................................................................................10 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12 1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12
TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 12
1.3 DATA LATENCY ............................................................................................................................................. 12
TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14
FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 14 TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 14 TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION) ............................................................... 14
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
TABLE 5: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 15 TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 16 2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 16 FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS............................................................................................................ 16
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 17
FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 17
2.5 LOSS OF SIGNAL .......................................................................................................................................... 17
FIGURE 7. LOS DECLARATION CIRCUIT........................................................................................................................................... 17
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 18 2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 18
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 18
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 19
FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 19
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 19 2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 20
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING ............................................................................................................................ 20 TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION) ......................................................................... 20 TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION) ........................................................................... 20 TABLE 9: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION .............................................................................................. 21
3.0 TRANSMIT SECTION ..........................................................................................................................22
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 22
FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 22
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 23
FIGURE 12. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 23 TABLE 10: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 23 TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION)........................................................................... 23
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 24
FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION) ...................................... 24
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 24
FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING............................................................................................................ 24 TABLE 12: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ...................................................... 25 TABLE 13: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION). ....................................................... 25
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L31
REV. 1.0.2
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 25
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
TABLE 14: CLOCK MULTIPLIER UNIT REQUIREMENTS FOR REFERENCE CLOCK .................................................................................. 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 27
TABLE 15: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS ................................................................................................. 27 FIGURE 16. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK ....................................................... 28
3.8 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
FIGURE 17. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 28
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 29
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 29
FIGURE 18. SERIAL REMOTE LOOPBACK......................................................................................................................................... 29
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 29
FIGURE 19. DIGITAL LOCAL LOOPBACK........................................................................................................................................... 29
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 30
FIGURE 20. ANALOG LOCAL LOOPBACK .......................................................................................................................................... 30
4.4 SPLIT LOOPBACK ......................................................................................................................................... 30
FIGURE 21. SPLIT LOOPBACK......................................................................................................................................................... 30
4.5 EYE DIAGRAM ............................................................................................................................................... 31
FIGURE 22. TRANSMIT ELECTRICAL OUTPUT EYE DIAGRAM............................................................................................................. 31
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 31
4.6.1 JITTER TOLERANCE: ................................................................................................................................................ 31 FIGURE 23. GR-253 JITTER TOLERANCE MASK .............................................................................................................................. 32 TABLE 16: XRT91L31 RECEIVER JITTER TOLERANCE PERFORMANCE............................................................................................. 32 FIGURE 24. XRT91L31 MEASURED JITTER TOLERANCE WITH 77.76MHZ REFERENCE CLOCK ......................................................... 32 FIGURE 25. XRT91L31 MEASURED JITTER TOLERANCE WITH 19.44MHZ REFERENCE CLOCK ......................................................... 33 4.6.2 JITTER TRANSFER .................................................................................................................................................... 33 FIGURE 26. XRT91L31 MEASURED JITTER TRANSFER WITH 77.76MHZ REFERENCE CLOCK ........................................................... 33 FIGURE 27. XRT91L31 MEASURED JITTER TRANSFER WITH 19.44MHZ REFERENCE CLOCK ........................................................... 34 4.6.3 JITTER GENERATION................................................................................................................................................ 34 TABLE 17: XRT91L31 OPTICAL JITTER GENERATION USING 223-1 PRBS PATTERN ........................................................................ 34 TABLE 18: XRT91L31 OPTICAL JITTER GENERATION USING 223-1 PRBS PATTERN USING ALTERNATE STANDARD FILTERS............. 34
5.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 36 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 36 ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ......................................................... 36 POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 36 ................................................................................................................................................................... 36 LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...................................... 37 ORDERING INFORMATION .................................................................................................................. 38
PACKAGE DIMENSIONS ................................................................................................ 38
REVISION HISTORY ...................................................................................................................................... 39
II
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
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REV. 1.0.2
PIN DESCRIPTIONS
HARDWARE CONTROL
NAME RESET LEVEL LVTTL, LVCMOS TYPE I PIN 1 DESCRIPTION Master Reset Input Active "High." When this pin is pulled "High" , the internal state machines are set to their default state. "Low" = Normal Operation "High" = Master Hardware Reset Data Rate Selection Selects SONET/SDH transmission and reception speed rate "Low" = STS-3/STM-1 155.52 Mbps "High" = STS-12/STM-4 622.08 Mbps Clock Multiplier Unit Reference Frequency Select This pin is used to select the frequency of the REFCLKP/N or TTLREFCLK input to the CMU. "Low" = 77.76 MHz reference clock "High" = 19.44 MHz reference clock
REFCLKP/N OR TTLREFCLK
REFERENCE FREQUENCY
STS12/STS3
LVTTL, LVCMOS
I
59
CMUFREQSEL
LVTTL, LVCMOS
I
3
CMUFREQSEL 0
STS12/ STS3 0
DATA RATE
77.76 MHz
STS-3/STM-1 155.52 Mbps STS-12/STM-4 622.08 Mbps STS-3/STM-1 155.52 Mbps STS-12/STM-4 622.08 Mbps
0
1
77.76 MHz
1
0
19.44 MHz
1
1
19.44 MHz
NOTE: REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for SONET systems.. CDR_BW/VDD LVTTL, LVCMOS I 15 CDR Bandwidth Select This pin is used to select the CDR Bandwidth "Low" = Narrow BW, (SONET Jitter Transfer and Jitter Tolerance) "High" (VDD) = Wide BW (Better jitter tolerance)
4
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REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
LEVEL LVTTL, LVCMOS TYPE I PIN 60 DESCRIPTION Clock and Data Recover Unit Reference Frequency Select Selects the Clock and Data Recovery Unit reference frequency based on the table below. "Low" = CDR uses CMU's reference clock "High" = CDR reference clock from CDRAUXREFCLK
CDRREFSEL STS12/ STS3 CDRAUXREFCLK FREQUENCY DATA RATE
NAME CDRREFSEL
0 1 0
CDR uses CMU's reference clock (see CMUFREQSEL pin) 77.76 MHz STS-3/STM-1 155.52 Mbps STS-12/STM-4 622.08 Mbps
1
1
77.76 MHz
NOTE: LOOPTIME LVTTL, LVCMOS I 2
CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 500ppm.
Loop Timing Mode When the loop timing mode is activated the external reference clock to the input of the Retimer is replaced with the high-speed recovered receive clock from the CDR. "Low" = Disabled "High" = Loop timing Activated Clock and Data Recovery Unit Disable Active "High." Disables internal Clock and Data Recovery unit. Received serial data bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of externally recovered differential clock XRXCLKIP/N coming from the optical module. "Low" = Internal CDR unit is Enabled "High" = Internal CDR unit is Disabled and Bypassed Transmit Parallel Clock Directional Control Transmit Parallel Clock Output Operation If this pin is asserted "High", TXPCLK_IO is a parallel bus clock output. Data on the TXDI[7:0] must be synchronously applied prior to the sampling by the PISO at the rising edge of TXPCLK_IO clock output driven by the XRT91L31. Alternate Transmit Parallel Clock Input Operation Asserting this control pin "Low" or if left unconnected, it configures TXPCLK_IO to serve as a parallel bus clock input rather than a parallel bus clock output and permits the XRT91L31 to accept the external clock input. Data on the TXDI[7:0] is then sampled at the rising edge of the TXPCLK_IO clock input driven by the framer/mapper device. "Low" = TXPCLK_IO is a Parallel Clock Input. "High" = TXPCLK_IO is a Parallel Clock Output. NOTE: Parallel Clock Input operation has the advantage of permitting the framer/mapper device timing to be synchronized with the transceiver transmitter timing.
CDRDIS
LVTTL, LVCMOS
I
12
PIO_CTRL
LVTTL, LVCMOS
I
48
This pin is provided with an internal pull-down.
5
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
NAME RLOOPS LEVEL LVTTL, LVCMOS TYPE I PIN 63 DESCRIPTION
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REV. 1.0.2
Serial Remote Loopback The serial remote loopback mode interconnects the receive serial data input to the transmit serial data output. If serial remote loopback is enabled, the 8-bit parallel transmit data input is ignored while the 8-bit parallel receive data output is maintained. "Low" = Disabled "High" = Serial Remote Loopback Mode Enabled NOTE: DLOOP and RLOOPS can be enabled simultaneously to achieve a dual loopback diagnostic feature in normal operation.
DLOOP
LVTTL, LVCMOS
I
62
Digital Local Loopback The digital local loopback mode interconnects the 8-bit parallel transmit data input and TxCLK to the 8-bit parallel receive data output and RxCLK respectively while maintaining the transmit serial data output. If digital local loopback is enabled, the receive serial data input is ignored. "Low" = Disabled "High" = Digital Local Loopback Mode Enabled NOTE: DLOOP and RLOOPS can be enabled simultaneously to achieve a dual loopback diagnostic feature in normal operation.
ALOOP
LVTTL, LVCMOS
I
64
Analog Local Loopback This loopback feature serializes the 8-bit parallel transmit data input and presents the data to the transmit serial output and in addition it also internally routes the serialized data back to the Clock and Data Recovery block for serial to parallel conversion. The received serial data input is ignored. "Low" = Disabled "High" = Analog Local Loopback Mode Enabled
6
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TRANSMITTER SECTION
NAME TXDI0 TXDI1 TXDI2 TXDI3 TXDI4 TXDI5 TXDI6 TXDI7 LEVEL LVTTL, LVCMOS TYPE I PIN 58 57 56 55 54 53 51 50 DESCRIPTION Transmit Parallel Data Input Transmit Parallel Clock Output Operation The 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1) 8-bit parallel transmit data should be applied to the transmit parallel bus and simultaneously referenced to the rising edge of the TXPCLK_IO clock output. The 8-bit parallel interface is multiplexed into the transmit serial output interface with the MSB first (TXDI[7:0]). Alternate Transmit Parallel Clock Input Operation When operating is this mode, TXPCLK_IO is no longer a parallel clock output reference but reverses direction and serves as the parallel transmit clock input reference for the PISO (Parallel Input to Serial Output) block. The 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1) 8-bit parallel transmit data should be applied to the transmit parallel bus and simultaneously referenced to the rising edge of the TXPCLK_IO clock input. TXOP TXON LVPECL Diff O 5 6 Transmit Serial Data Output The transmit serial data stream is generated by multiplexing the 8-bit parallel transmit data input into a 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 serial data stream. Transmit Parallel Clock Input/Output (77.76/19.44 MHz) Transmit Parallel Clock Output Operation When the PIO_CTRL pin 48 is asserted "High," this pin will output a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM1) clock output reference for the 8-bit parallel transmit data input TXDI[7:0]. This clock is used by the framer/mapper device to present the TXDI[7:0] data which the XRT91L31 will latch on the rising edge of this clock. This enables the framer/mapper device and the XRT91L31 transceiver to be in synchronization. Alternate Transmit Parallel Clock Input Operation When the PIO_CTRL pin 48 is asserted "Low," this pin will accept a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/ STM-1) clock input reference for the 8-bit parallel transmit data input TXDI[7:0]. The XRT91L31 will latch data at TXDI[7:0] on the rising edge of this clock. This has the enormous advantage of enabling the framer/mapper device transmit timing to be synchronized with the transceiver transmit timing.
TXPCLK_IO
LVTTL, LVCMOS
I/O
49
7
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TRANSMITTER SECTION
NAME REFCLKP REFCLKN LEVEL LVPECL Diff TYPE I PIN 16 17 DESCRIPTION
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REV. 1.0.2
Reference Clock Input (77.76 MHz or 19.44 MHz) This differential clock input reference is used for the transmit clock multiplier unit (CMU) and clock data recovery (CDR) to provide the necessary high speed clock reference for this device. It will accept either a 77.76 MHz or a 19.44 MHz Differential LVPECL clock source. Pin CMUFREQSEL determines the value used as the reference. See Pin CMUFREQSEL for more details. REFCLKP/N inputs are internally biased to 1.65V. NOTE: In the event that TTLREFCLK LVTTL input is used instead of these differential inputs for clock reference, the REFCLKP should be tied to ground.
TTLREFCLK
LVTTL, LVCMOS
I
36
Auxillary Reference Clock Input (77.76 MHz or 19.44 MHz) This LVTTL clock input reference is used for the transmit clock multiplier unit (CMU) and clock data recovery (CDR) to provide the necessary high speed clock reference for this device. It will accept either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin CMUFREQSEL determines the value used as the reference. See Pin CMUFREQSEL for more details. NOTE: In the event that REFCLKP/N differential inputs is used instead of this LVTTL input for clock reference, the TTLREFCLK should be tied to ground.
8
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
RECEIVER SECTION
NAME RXDO0 RXDO1 RXDO2 RXDO3 RXDO4 RXDO5 RXDO6 RXDO7 RXIP RXIN LEVEL LVTTL, LVCMOS TYPE O PIN 19 20 22 23 24 25 26 27 13 14 DESCRIPTION Receive Parallel Data Output 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1) 8-bit parallel receive data output is updated simultaneously on the falling edge of the RXPCLKO output. The 8-bit parallel interface is de-multiplexed from the receive serial data input MSB first (RXDO[7]). The XRT91L31 will output the data on the falling edge of RXPCLKO clock.
Diff LVPECL
I
Receive Serial Data Input The differential receive serial data stream of 622.08 Mbps STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to these input pins. External Recovered Receive Clock Input The differential receive serial data stream of 622.08 Mbps STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on the rising edge of this externally recovered differential clock coming from the optical module. It is used when the internal CDR unit is disabled and bypassed by the CDRDIS pin. NOTE: In the event that XRXCLKIP/N differential input pins are unused, XRXCLKIP should be tied to VCC with a 1k Ohm pull-up and XRXCLKIN should be tied to Ground with a 1k Ohm pull-down.
XRXCLKIP XRXCLKIN
Diff LVPECL
I
8 9
RXPCLKO
LVTTL, LVCMOS
O
29
Receive Parallel Clock Output (77.76 MHz or 19.44 MHz) 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1) clock output reference for the 8-bit parallel receive data output RXDO[7:0]. The parallel received data output bus will be updated on the falling edge of this clock. Clock and Data Recovery Auxillary Reference Clock 77.76 MHz 500 ppm auxillary reference clock for the CDR. NOTE: In the event that CDRAUXREFCLK LVTTL input pin is unused, CDRAUXREFCLK should be tied to ground.
CDRAUXREFCLK
LVTTL, LVCMOS
I
32
OOF
LVTTL, LVCMOS
I
11
Out of Frame Input Indicator This level sensitive input pin is used to initiate frame detection and byte alignment recovery when OOF is declared by the downstream device. When this pin is held High, FRAMEPULSE will pulse for a single RXPCLKO period upon the detection of every third frame alignment A2 byte in the incoming SONET/SDH Frame. "Low" = Normal Operation "High" = OOF Indication initiating frame detection and byte boundary recovery and activating FRAMEPULSE Sonet Frame Alignment Pulse This pin will generate a single pulse for an RXPCLKO clock period upon the detection of the third frame alignment A2 byte whenever the OOF input pin is held High. The parallel received data output bus will then be byte aligned to this newly recovered SONET/SDH frame.
FRAMEPULSE
LVTTL, LVCMOS
O
30
9
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
NAME CAP1P CAP2P LEVEL Analog TYPE PIN 39 42 DESCRIPTION
xr
REV. 1.0.2
CDR Non-polarized External Filter Capacitor C1 = 0.47F 10% tolerance (Isolate from noise and place close to pin) CDR Non-polarized External Filter Capacitor C2 = 0.47F 10% tolerance (Isolate from noise and place close to pin) LOS (Los of Signal) Detect Disable Disables internal LOS monitoring and automatic muting of RXDO[7:0] upon LOS detection. LOS is declared when a string of 128 consecutive zeros occur on the line. LOS condition is cleared when the 16 or more pulse transitions is detected for 128 bit period sliding window (see Figure 7.) "Low" = Monitor and Mute received data upon LOS declaration "High" = Disable internal LOS monitoring LOS or Signal Detect Input from Optical Module Active "Low." When active, this pin can force the received data output bus RXDO[7:0] to a logic state of '0' per Figure 7. "Low" = Forced LOS "High" = Normal Operation
CAP1N CAP2N
Analog
-
40 41
DLOSDIS
LVTTL, LVCMOS
I
7
LOSEXT
SE-LVPECL
I
33
POWER AND GROUND
NAME VDD3.3 TYPE PWR PIN 18, 31, 34, 47, 61 DESCRIPTION 3.3V CMOS Power Supply VDD3.3 should be isolated from the Analog VDD power supplies. Use a ferrite bead along with an internal power plane separation. The VDD3.3 power supply pins should have bypass capacitors to the nearest ground. Analog 3.3V Transmitter Power Supply AVDD3.3_TX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD3.3_TX power supply pins should have bypass capacitors to the nearest ground. Analog 3.3V Receiver Power Supply AVDD3.3_RX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD3.3_RX power supply pins should have bypass capacitors to the nearest ground. 3.3V Input/Output LVPECL Bus Power Supply These pins require a 3.3V potential voltage for properly biasing the Differential LVPECL input and output pins. Transmitter Analog Ground for 3.3V Analog Power Supplies It is recommended that all ground pins of this device be tied together.
AVDD3.3_TX
PWR
38
AVDD3.3_RX
PWR
43
VDD_PECL
PWR
4, 10
AGND_TX
PWR
37
10
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TYPE PWR PIN 44 DESCRIPTION Receiver Analog Ground for 3.3V Analog Power Supplies It is recommended that all ground pins of this device be tied together. Power Supply and Thermal Ground It is recommended that all ground pins of this device be tied together.
NAME AGND_RX
GND
GND
21, 28, 35, 45, 46, 52
11
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 1.0 FUNCTIONAL DESCRIPTION
xr
REV. 1.0.2
The XRT91L31 transceiver is designed to operate with a SONET Framer/ASIC device and provide a highspeed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622.08 Mbps or 155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/deserialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to provide the front end component of SONET equipment, which includes primarily serial transmit and receive functions. 1.1 STS-12/STM-4 and STS-3/STM-1 Mode of Operation Functionality of the transceiver can be configured by using the appropriate signal level on the STS-12/STS-3 pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High." Therefore, the following sections describe the functionality rather than how each function is controlled. Hence, the Hardware Pin and Register Bit Descriptions focus on device configuration. 1.2 Clock Input Reference for Clock Multiplier (Synthesizer) Unit The XRT91L31 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP/N or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for SONET systems. The reference clock can be provided with one of two frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L31 are listed in Table 1. TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) CMUFREQSEL 0 0 1 1 STS12/STS3 0 1 0 1 REFCLKP/N OR TTLREFCLK
REFERENCE FREQUENCY
DATA RATE STS-3/STM-1 155.52 Mbps STS-12/STM-4 622.08 Mbps STS-3/STM-1 155.52 Mbps STS-12/STM-4 622.08 Mbps
77.76 MHz 77.76 MHz 19.44 MHz 19.44 MHz
1.3
Data Latency
Due to different operating modes and data logic paths through the device, there is an associated latency from data ingress to data egress. Table 2 specifies the data latency for a typical path. TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY
MODE OF OPERATION
Thru-mode
DATA PATH
MSB at RXIP/N to data on RXDO[7:0]
CLOCK REFERENCE RANGE OF CLOCK CYCLES
Recoved RXIP/N Clock Recoved RXIP/N Clock 25 to 35 2 to 4
Serial Remote Loopback MSB at RXIP/N to MSB at TXOP/N
12
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.0 RECEIVE SECTION The receive section of XRT91L31 include the inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ) serial data at 622.08 Mbps or 155.52 Mbps through the input interfaces RXIP/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered serial data is converted into an 8-bit-wide, 77.76 Mbps or 19.44 Mbps parallel data and presented to the RXDO[7:0] parallel interface. This parallel interface is designed for Single-Ended LVTTL operation. A divideby-8 version of the high-speed recovered clock RXPCLKOP/N, is used to synchronize the transfer of the 8-bit RXDO[7:0] data with the receive portion of the framer/mapper device. Upon initialization or loss of signal or loss of lock, the external reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock recovery phase-locked loop for proper operation. In certain applications, the CDR block on the XRT91L31 can be disabled and bypassed by enabling the CDRDIS pin to permit the flexibility of using an externally recovered receive clock thru the XRXCLKIP/N pins. 2.1 Receive Serial Input The receive serial inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an optical module or an electrical interface. See Applications note for further clarifications. A simplified DC FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK
Install terminators as close to RXIP and RXIN pins
120 RXIP RXIN
XRT91L31 STS-12/STM-4 or STS-3/STM-1 Transceiver XRXCLKIP XRXCLKIN
Optical Module Optical Fiber 82 1k
Tie unused differential input pins to VCC and GND
1k (optional)
coupling block diagram is shown in Figure 3.
NOTE: Some optical modules integrate AC coupling capacitors within the module. AC or DC coupling is largely specific to system design and optical module of choice.
13
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.2 Recieve Serial Data Input Timing
xr
REV. 1.0.2
The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing specifications below. FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM
tRXCLK
XRXCLKIP XRXCLKIN
tRX_SU RXIP RXIN
tRX_HD
TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL tRXCLK tRX_SU tRX_HD PARAMETER Receive external recovered clock period Serial data setup time with respect to XRXCLKIP/N Serial data hold time with respect to XRXCLKIP/N 400 100 MIN TYP 1.608 MAX UNITS ns ps ps
TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL tRXCLK tRX_SU tRX_HD PARAMETER Receive external recovered clock period Serial data setup time with respect to XRXCLKIP/N Serial data hold time with respect to XRXCLKIP/N 1.5 1.5 MIN TYP 6.43 MAX UNITS ns ns ns
14
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.3
Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL receiver and generates a clock that is the same frequency as the incoming data. The clock recovery can either utilize the transmitter's CMU reference clock from either REFCLKP/N or TTLREFCLK or it can use independent clock source CDRAUXREFCLK to train and monitor its clock recovery PLL. Initially upon startup, the PLL locks to the local reference clock within 500 ppm. Once this is achieved, the PLL then attempts to lock onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a receive clock (based on the local reference) to the framer/mapper device. When the LOSEXT is asserted by the optical module or when LOS is detected, the receive parallel data output will be forced to a logic zero state for the entire duration that a LOS condition is detected. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the LOSEXT becomes inactive and the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back onto the incoming receive data stream. Table 5 shows Clock and Data Recovery reference clock settings. Table 6 specifies the Clock and Data Recovery Unit performance characteristics. TABLE 5: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS
STS12/ STS3 0 1 0 1 0 1 REFCLKP/N1OR TTLREFCLK1 FREQUENCY (MHZ)
77.76 MHz 77.76 MHz 19.44 MHz 19.44 MHz
CMUFREQSEL CDRREFSEL
CDRAUXREFCLK2 FREQUENCY (MHZ) not used not used not used not used
77.76 MHz 77.76 MHz
CDR OUTPUT FREQUENCY (MHZ)
155.52 622.08 155.52 622.08 155.52 622.08
0 0 1 1 X X
1
0 0 0 0 1 1
not referenced by CDR not referenced by CDR
Requires frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for SONET systems. CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 500ppm.
2
15
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE
NAME
REFDUTY REFJIT REFJIT REFTOL OCLKFREQ OCLKDUTY
1
xr
REV. 1.0.2
PARAMETER
Reference clock duty cycle Reference clock jitter (rms) with 19.44 MHz reference1 Reference clock jitter (rms) with 77.76 MHz reference1 Reference clock frequency tolerance2 Frequency output Clock output duty cycle
MIN 40
TYP
MAX 60 5 13
UNITS % ps ps ppm MHz %
-20 620 40
+20 624 60
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms). to meet SONET output frequency stability requirements.
2Required
2.3.1
Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock. Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5 shows the possible internal paths of the recovered clock and data. FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS
CLOCK CDRDIS
MUX
XRXCLKIP XRXCLKIN Clk CDR Data RXIP RXIN
SIPO Parallel DATA 8
DATA
MUX
Div by 8 CLOCK
16
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.4
External Receive Loop Filter Capacitors
These external loop filter 0.47F non-polarized capacitors provide the necessary components to achieve the required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and should be placed as close to the pins as much as possible. Figure 6 shows the pin connections and external loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance. FIGURE 6. EXTERNAL LOOP FILTERS
0.47uF
non-polarized
0.47uF
non-polarized
pin 39
pin 42
pin 40
pin 41
CAP1P
CAP2P
CAP1N
CAP2N
2.5
Loss Of Signal
XRT91L31 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of Signal Detector monitors the incoming data stream and if the incoming data stream has no transition continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output usually called "SD" or "FLAG" which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High". LOSEXT is an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin and internal LOS detector are gated to control detection and declaration of Loss of Signal (see Figure 7.) Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, and none of the local loopback loops is enabled, the XRT91L31 will automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOS condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the local FIGURE 7. LOS DECLARATION CIRCUIT
DLOS (internal signal) DLOSDIS RLOOPS RLPS_D_MUTE
LOSEXT' ALOOP DLOOP
`0' = No LOS detection => Do not mute receive parallel data bus `1' = LOS_detection => Mute Receive data bus
loopbacks DLOOP and ALOOP are enabled, then LOS conditions will not mute the RX parallel output.
17
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.2
During RLOOPS operation, the 91L31 mutes the RLOOPS data going to Tx output upon detection of DLOS while DLOSDIS is not enabled. During RLOOPS operation, the 91L31 also mutes the RLOOPS data going to Tx output while the LOSEXT input is set to a "LOW" state. Note that the DLOSDIS control pin has no impact on the CDR muting function due to LOSEXT. DLOSDIS only applies to muting as a result of DLOS detection. Also, note that the muting function only impacts the RLOOPS data going to Tx output, and the CDR clock output & RLOOPS clock going to Tx block shall remain active (see Figure 7.) 2.6 SONET Frame Boundary Detection and Byte Alignment Recovery A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1 (0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The detector operates under the control of the OOF (Out of Frame) signals provided from the SONET Framer. Detection is enabled when OOF is held "High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-toparallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse (FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern matching the framing pattern is detected on the incoming data stream. While in the pattern search and detection state and so long is OOF is active, the frame pulse (FRAMEPULSE) output is activated for one byte clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/ STM-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. Once the SONET Framer Overhead Circuitry has verified that frame and byte synchronization are correct, the OOF input pin should be de-asserted by the SONET Framer to disable the XRT91L31 frame search process from trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L31's framing pattern detection is disabled upon the de-assertion of OOF input pin from the SONET Framer, the byte boundary will lock to the detected location and will remain locked to that location found when detection was previously enabled. 2.7 Receive Serial Input to Parallel Output (SIPO) During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L31 is operating in STS-3/ STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is shown in Figure 8. XRT91L31 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO. FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO
8-bit Parallel LVTTL Output Data RXDO0 b03 b02 b01 b00
SIPO
RXDOn
bn3 bn2 bn1 bn0
622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 serial data rate b73 b63 b53 b43 b33 b23 b13 b70 b60 b50 b40 b30 b20 b10 b00 RXIP/N
RXDOn+
bn+3 bn+2 bn+1 bn+0
RXDO7
b73 b72 b71 b70
RXPCLKO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
18
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.8
Receive Parallel Output Interface
The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered clock. A simplified block diagram is shown in Figure 9. FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK
RXDO[7:0]
8
RXPCLKO
XRT91L31 STS-12/STM-4 or STS-3/STM-1 Transceiver
SONET Framer/ASIC
2.9
Disable Parallel Receive Data Output Upon LOS
The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS condition (DLOOP or ALOOP not activated) to prevent data chattering unless LOS detection is disabled by asserting DLOSDIS and keeping LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin from the optical module to force an LOS and mute the parallel receiver outputs as well when DLOSDIS is not enabled (LOW), see Figure 7).
19
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.10 Receive Parallel Data Output Timing
xr
REV. 1.0.2
The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and hold times shown in Figure 10 ,Table 7, and Table 8. Table 9 shows the PECL and TTL output timing specifications. FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING
tRXCLK RXIP RXIN tRXPCLKO
RXPCLKO
RXDO[7:0]
A1
A2
A2
A2 tRXDO_VALID
A2
FRAMEPULSE
tPULSE_WID
TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL PARAMETER MIN TYP MAX UNITS
tRXCLK tRXPCLKO tRXDO_VALID tPULSE_WID
Receive high-speed serial clock period Receive parallel data output byte clock period Time the data is valid on RXDO[7:0] and FRAMEPULSE before and after the rising edge of RXPCLKO Pulse width of frame detection pulse on FRAMEPULSE 4
1.608 12.86
ns ns ns
12.86
ns
TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL PARAMETER MIN TYP MAX UNITS
tRXCLK tRXPCLKO tRXDO_VALID tPULSE_WID
Receive high-speed serial clock period Receive parallel data output byte clock period Time the data is valid on RXDO[7:0] and FRAMEPULSE before and after the rising edge of RXPCLKO Pulse width of frame detection pulse on FRAMEPULSE 22
6.43 51.44
ns ns ns
51.44
ns
20
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TABLE 9: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tR_PECL tF_PECL tR_TTL tF_TTL
PECL output rise time (20% to 80%) PECL output fall time (80% to 20%) TTL output rise time (10% to 90%) TTL output fall time (90% to 10%)
350 350 2 1.5
ps ps ns ns
21
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION
xr
REV. 1.0.2
The transmit section of the XRT91L31 accepts 8-bit parallel data and converts it to serial Differential LVPECL data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL interface, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Low Voltage Positive-referenced Emitter-Coupled Logic (LVPECL) differential line driver, and Loop Timing modes. The LVPECL serial data output rate is 622.08 Mbps for STS-12/STM-4 applications and 155.52 Mbps for STS-3/STM-1 applications. The high frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In order to synchronize the data transfer process, the synthesized 622.08 MHz for STS-12/STM-4 or 155.52 MHz STS-3/STM-1 serial clock output is divided by eight and the 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1) clock respectively is presented to the framer/mapper device to be used as its timing source. 3.1 Transmit Parallel Input Interface The parallel data from an framer/mapper device is presented to the XRT91L31 through an 8-bit Single-Ended LVTTL parallel bus interface TXDI[7:0]. To directly interface to the XRT91L31, the SONET Framer/ASIC must be synchronized to the same timing source TXPCLK_IO in presenting data on the parallel bus interface. The data must meet setup and hold times with respect to TXPCLK_IO. This clock output source is used to synchronize the SONET Framer/ASIC to the XRT91L31. The framer/mapper device should use TXPCLK_IO as its timing source so that parallel data is phase aligned with the serial transmit data. The data is latched into a parallel input register on the rising edge of TXPCLK_IO. TXPCLK_IO is derived from a divide-by-8 of the high speed synthesized clock resulting in a 77.76/ 19.44 MHz Single-Ended LVTTL clock output source to be used by the framer/mapper device for parallel bus synchronization. A simplified block diagram of the transmit parallel bus clock output system interface is shown in Figure 11. FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK
TXDI[7:0]
8 TXPCLK_IO
XRT91L31 STS-12/STM-4 or STS-3/STM-1 Transceiver
SONET Framer/ASIC
VDD+
PIO_CTRL
CMUREFSEL REFCLKN REFCLKP
TTLREFCLK
22
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.2
Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 12 and Table 10, Table 11. FIGURE 12. TRANSMIT PARALLEL INPUT TIMING
Transmit Parallel Clock Output
tTXPCLK_IO
Transmit Parallel Clock driven by XRT91L31 Device
TXPCLK_IO
tTXDI_HD tTXDI_SU TXDI[7:0]
TABLE 10: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL PARAMETER MIN TYP MAX UNITS
tTXPCLK_IO tTXDI_SU tTXDI_HD
Transmit Clock Output period Transmit data setup time with respect to TXPCLK_IO Transmit data hold time with respect to TXPCLK_IO 1.0 1.0
12.86
ns ns ns
TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION).
SYMBOL PARAMETER MIN TYP MAX UNITS
tTXPCLK_IO tTXDI_SU tTXDI_HD
Transmit Clock Output period Transmit data setup time with respect to TXPCLK_IO Transmit data hold time with respect to TXPCLK_IO 1.0 1.0
51.44
ns ns ns
23
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.3 Alternate Transmit Parallel Bus Clock Input Option
xr
REV. 1.0.2
To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L31 transceiver and to eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be optionally configured as a clock input. Rather than provide a transmit parallel clock output reference to the framer/ mapper device, the XRT91L31 can instead accept a reference transmit parallel clock input signal from the framer/mapper device to sample the transmit parallel bus. When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO switches into a clock input and the XRT91L31 will now sample data on the transmit parallel bus TXDI[7:0] based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing. Figure 13 provides a detailed overview of the alternate transmit parallel bus clock input system interface. FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION)
TXDI[7:0]
8 TXPCLK_IO
(Parallel Clock Input Option)
XRT91L31 STS-12/STM-4 or STS-3/STM-1 Transceiver
SONET Framer/ASIC
CMUREFSEL REFCLKN REFCLKP TTLREFCLK
PIO_CTRL
3.4
Alternate Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of operation, the setup and hold times should be followed as shown in Figure 14 and Table 12, Table 13. FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING
Transmit Parallel Clock driven by Framer/Mapper Device
TXPCLK_IO
Alternate Transmit Parallel Clock Input Option
tTXPCLK_IO
tTXDI_HD tTXDI_SU TXDI[7:0]
24
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE 12: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL PARAMETER MIN TYP MAX UNITS
tTXPCLK_IO tTXDI_SU tTXDI_HD
Transmit Clock Input period Transmit data setup time with respect to TXPCLK_IO Transmit data hold time with respect to TXPCLK_IO 1.0 1.0
12.86
ns ns ns
TABLE 13: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION).
SYMBOL PARAMETER MIN TYP MAX UNITS
tTXPCLK_IO tTXDI_SU tTXDI_HD
Transmit Clock Input period Transmit data setup time with respect to TXPCLK_IO Transmit data hold time with respect to TXPCLK_IO 1.0 1.0
51.44
ns ns ns
3.5
Transmit Parallel Input to Serial Output (PISO)
The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI7, then the first bit from TXDI6, and so on as shown in Figure 15. FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF PISO
8-bit Parallel LVTTL Input Data TXDI0 b07 b06 b05 b04 b03 b02 b01 b00 time (0) TXDIn bn7 bn6 bn5 bn4 bn3 bn2 bn1 bn0 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 serial data rate b70 b60 b50 b40 b30 b20 b77 b67 b57 b47 b37 b27 b17 b07 TXOP/N
TXDIn+
bn+7 bn+6 bn+5 bn+4 bn+3 bn+2 bn+1 bn+0
TXDI7
b77 b76 b75 b74 b73 b72 b71 b70
TXPCLK_IO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
PISO
25
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.6 Clock Multiplier Unit (CMU) and Re-Timer
xr
REV. 1.0.2
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed 622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for SONET systems. If the TTLREFCLK reference clock is used, the TTLREFCLK reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are XNOR'ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or TTLREFCLK to ground. Table 1, on page 12 shows the CMU reference clock frequency settings. Table 14 specifies the Clock Multiplier Unit requirements for reference clock. TABLE 14: CLOCK MULTIPLIER UNIT REQUIREMENTS FOR REFERENCE CLOCK
NAME
REFDUTY REFJIT REFJIT REFTOL OCLKFREQ OCYCDUTY Reference clock duty cycle Reference clock jitter (rms) with 19.44 MHz reference1 Reference clock jitter (rms) with 77.76 MHz reference1 Reference clock frequency tolerance2 Frequency output Clock output duty cycle ('1010' data pattern)
PARAMETER
MIN
TYP
MAX
UNITS
40
60 5 13
% ps ps ppm MHz %
-20 620 45
+20 624 55
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1 2
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms). Required to meet SONET output frequency stability requirements.
26
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REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.7
Loop Timing and Clock Control
Two types of loop timing are possible in the XRT91L31. In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is selected by asserting the LOOPTIME signal to a high level. When the loop timing mode is activated, the CMU synthesized hi-speed reference clock input to the Retimer is replaced with the hi-speed internally recovered receive clock coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the internally recovered receive clock. Loop time mode directly locks the Retimer to the recovered receive clock. In external loop timing mode, the XRT91L31 allows the user the flexibility of using an externally recovered receive clock for retiming the high speed serial data. First, the CDRDIS input pin should be set high. By doing so, the internal CDR is disabled and bypassed and the XRT91L31 will sample the incoming high speed serial data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state, the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L31 will sample RXIP/N on the rising edge of XRXCLKIP/N. Secondly, the LOOPTIME pin must also be set high in order to select the externally recovered receive clock on XRXCLKIP/N as the reference clock source for the transmit serial data output stream TXOP/N. Table 15 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip CDR or an external recovered clock in loop timing applications is shown in Figure 16. TABLE 15: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS
CDRDIS 0 0 LOOPTIME 0 1 TRANSMIT CLOCK SOURCE
Clock Multiplier Unit
RECEIVE CLOCK SOURCE
CDR Enabled. Clock and Data recovery by internal CDR CDR Enabled. Clock and Data recovery by internal CDR CDR Disabled. Externally recovered Receive Clock from XRXCLKIP/N 622.08/155.52 Mbps data on RXIP/N sampled at rising edge of XRXCLKIP/N CDR Disabled. Externally recovered Receive Clock from XRXCLKIP/N 622.08/155.52 Mbps data on RXIP/N sampled at rising edge of XRXCLKIP/N
Internal CDR
1
0
Clock Multiplier Unit
1
1
External CDR thru XRXCLKIP/N
27
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.2
FIGURE 16. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK
REFCLKP REFCLKN TTLREFCLK
XRT91L31
622.08/ 155.52MHz CMU MUX
DATA TXDI[7:0] TXPCLK_IO
ENB
PISO 8
0
MUX
CLK Div by 8
to Retimer
Retimer
TXOP TXON
1
ENB
PIO_CTRL LOOPTIME CDRDIS
MUX
XRXCLKIP XRXCLKIN Clk CDR RXIP RXIN
CLK
~
RXPCLKO Div by 8
MUX
RXDO[7:0] 8 SIPO DATA
Data
~
3.8
Transmit Serial Output Control
The 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 transmit serial output is avaliable on TXOP/N pins. The transmit serial output can be AC or DC coupled to an optical module or electrical interface. A simplified DC coupling block diagram is shown in Figure 17. FIGURE 17. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK
VDD 120 TXOP TXON Optical Module Optical Fiber
Install terminators as close to optical module transmit pins
XRT91L31 STS-12/STM-4 or STS-3/STM-1 Transceiver
82
NOTE: Some optical modules integrate AC coupling capacitors within the module. AC or DC coupling is largely specific to system design and optical module of choice.
28
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REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at the high speed transmit output TXOP/N, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input of the Retimer. During serial remote loopback, the high-speed receive data (RXIP/N) is also converted to parallel data and presented at the low-speed receive parallel interface RXDO[7:0]. The recovered receive clock is also divided by 8 and presented at the low-speed clock output RXPCLKO to synchronize the transfer of the 8-bit received parallel data. A simplified block diagram of serial remote loopback is shown in Figure 18. FIGURE 18. SERIAL REMOTE LOOPBACK
Serial Remote Loopback PISO Re-Timer LVPECL Output Drivers Tx Serial Output
Rx Parallel Output SIPO CDR LVPECL Input Drivers
Rx Serial Input
4.2
Digital Local Loopback
The digital local loopback is activated when the DLOOP signal is set "High." When digital local loopback is activated, the high-speed data from the output of the parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to parallel converter. The CMU output is also looped back to the receive section and is used to synchronize the transfer of the data through the receiver. In Digital loopback mode, the transmit data from the transmit parallel interface TXDI[7:0] is serialized and presented to the highspeed transmit output TXOP/N using the high-speed 622.08/155.52 MHz transmit clock generated from the clock multiplier unit and presented to the input of the Retimer and SIPO. A simplified block diagram of digital loopback is shown in Figure 19. FIGURE 19. DIGITAL LOCAL LOOPBACK
Digital Loopback Tx Parallel Input PISO Re-Timer LVPECL Output Drivers Tx Serial Output
Rx Parallel Output SIPO CDR LVPECL Input Drivers
29
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.3 Analog Local Loopback
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REV. 1.0.2
Analog Local Loopback (ALOOP) controls a more comprehensive version of digital local loopback in which the point where the transmit data is looped back is moved all the way back to the high-speed receive I/O. The transmit data from the transmit parallel interface TXDI[7:0] is serialized and presented to the high-speed transmit output TXOP/N using the high-speed 622.08/155.52 MHz transmit clock generated from the clock multiplier unit. In addition, the high-speed transmit data TXOP/N is looped back to the receive clock and data recovery unit, replacing the RXIP/N. The signal is then processed by the CDR, and is sent through the serial to parallel converter and presented at the low-speed receive parallel interface RXDO[7:0]. ALOOP is invoked by asserting the ALOOP pin "High." A simplified block diagram of parallel remote loopback is shown in Figure 20. FIGURE 20. ANALOG LOCAL LOOPBACK
Analog Local Loop back Tx Parallel Input PISO Re-Timer LVPECL Output Drivers Tx Serial Output
Rx Parallel Output SIPO CDR LVPECL Input Drivers
4.4
Split Loopback
The serial remote loopback and the digital local loopback can be combined to form a split loopback. The output of the parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to parallel converter. The high-speed serial receive data from RXIP/N is presented at the high speed transmit output TXOP/N, and the high-speed recovered clock is selected to re-time the high speed transmit data output. A simplified block diagram of parallel remote loopback is shown in Figure 21. FIGURE 21. SPLIT LOOPBACK
Split Loopback Tx Parallel Input PISO Re-Timer LVPECL Output Drivers Tx Serial Output
Rx Parallel Output SIPO CDR LVPECL Input Drivers
Rx Serial Input
30
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
4.5
Eye Diagram
The XRT91L31 Eye diagram illustrates the transmit serial output signal integrity and quality. FIGURE 22. TRANSMIT ELECTRICAL OUTPUT EYE DIAGRAM STS-3/STM-1 STS-12/STM-4
4.6
SONET Jitter Requirements
SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below. SONET equipment jitter requirements are specified for the following three types of jitter. 4.6.1 Jitter Tolerance: Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input OC-N equipment interface that causes an equivalent 1dB optical power penalty. OC-1/STS-1, OC-3/STS-3, OC-12 and OC-48 category II SONET interfaces should tolerate, the input jitter applied according to the mask of Figure 23, with the corresponding parameters specified in the figure.
31
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FIGURE 23. GR-253 JITTER TOLERANCE MASK
xr
REV. 1.0.2
A3 slope= -20dB/decade Input Jitter Amplitude (UIpp) A2 slope= -20dB/decade
A1
f0
f1
f2
f3
f4
Jitter Frequency (Hz)
OC-N/STS-N LEVEL 1 3 12 48
F0 (HZ) 10 10 10 10
F1 (HZ) 30 30 30 600
F2 (HZ) 300 300 300 6000
F3 (HZ) 2K 6.5K 25K 100K
F4 (HZ) 20K 65K 250K 1000K
A1 (UIPP) 0.15 0.15 0.15 0.15
A2 (UIPP) 1.5 1.5 1.5 1.5
A3 (UIPP) 15 15 15 15
TABLE 16: XRT91L31 RECEIVER JITTER TOLERANCE PERFORMANCE
FREQUENCY BAND INTERVAL INTERFACE LOW HIGH GR-253/ G.783 MINIMUM PERMISSIBLE LIMIT XRT91L31 JITTER TOLERANCE
MINIMUM
TYPICAL
MAXIMUM
OPTICAL
(KHZ)
(MHZ)
UI p2p 0.15 0.15
UI p2p 0.3 0.3
UI p2p 0.4 0.4
UI p2p
OC3/STM1 OC12/STM4
65 250
1 5
FIGURE 24. XRT91L31 MEASURED JITTER TOLERANCE WITH 77.76MHZ REFERENCE CLOCK STS-3/STM-1 STS-12/STM-4
32
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REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
FIGURE 25. XRT91L31 MEASURED JITTER TOLERANCE WITH 19.44MHZ REFERENCE CLOCK STS-3/STM-1 STS-12/STM-4
4.6.2
Jitter Transfer
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a low bandwidth loop. The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter. The jitter attenuator within the XRT91L31 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 26. FIGURE 26. XRT91L31 MEASURED JITTER TRANSFER WITH 77.76MHZ REFERENCE CLOCK STS-3/STM-1 STS-12/STM-4
33
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FIGURE 27. XRT91L31 MEASURED JITTER TRANSFER WITH 19.44MHZ REFERENCE CLOCK STS-3/STM-1 STS-12/STM-4
xr
REV. 1.0.2
4.6.3
Jitter Generation
Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The bandwidth is set according to the data rate. The Bellcore and ITU requirement for this type jitter is 0.01UI rms measured with a specific band-pass filter. For more information on these specifications refer to Bellcore TR-NWT-000253 sections 5.6.2-5 and GR-253CORE section 5.6 and ITUT G.783 section 9.3.1.1. Table 17 below shows the jitter generation limits per BellCore GR-253 and ITUT G.783 versus XRT91L31 typical jitter performance. TABLE 17: XRT91L31 OPTICAL JITTER GENERATION USING 223-1 PRBS PATTERN
MEASUREMENT BAND FILTER -3dB FREQUENCIES INTERFACE HIGH PASS OPTICAL (KHZ) LOW PASS (MHZ) GR-253/ G.783 MAXIMUM PERMISSIBLE LIMIT XRT91L31 INTRINSIC JITTER (TRANSMIT PARALLEL CLOCK INPUT DIRECTION) 19.44 MHZ REF CLOCK 77.76 MHZ REF CLOCK XRT91L31 INTRINSIC JITTER (TRANSMIT PARALLEL CLOCK OUTPUT DIRECTION) 19.44 MHZ REF CLOCK 77.76 MHZ REF CLOCK
mUI rms 10 10
mUI rms
mUI rms 2 7
mUI rms 2 8
mUI rms 2 7
OC3/STM1 OC12/STM4
12 12
1.3 5
TABLE 18: XRT91L31 OPTICAL JITTER GENERATION USING 223-1 PRBS PATTERN USING ALTERNATE STANDARD FILTERS
MEASUREMENT BAND FILTER -3dB FREQUENCIES INTERFACE HIGH PASS OPTICAL (KHZ) LOW PASS (MHZ) XRT91L31 INTRINSIC JITTER (TRANSMIT PARALLEL CLOCK INPUT DIRECTION) 19.44 MHZ REF CLOCK 77.76 MHZ REF CLOCK XRT91L31 INTRINSIC JITTER (TRANSMIT PARALLEL CLOCK OUTPUT DIRECTION) 19.44 MHZ REF CLOCK 77.76 MHZ REF CLOCK
mUI rms
mUI rms 2 4
mUI rms 1 5
mUI rms 2 4
OC3/STM1 OC12/STM4
65 250a
1.3 5
a. According to ITU-T G.783
34
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
35
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Thermal Resistance of QFP Package........jA = 45C/W Thermal Resistance of QFP Package........jC = 12C/W ESD Protection (HBM)..........................................>2000V
xr
REV. 1.0.2
Operating Temperature Range.................-40C to 85C Case Temperature under bias..................-55C to 125C Storage Temperature ...............................-65C to 150C
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS
SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS
VDD3.3 VDDLVPECL AVDD_IO LVPECL LVTTL LVTTL LVPECL LVTTL
CMOS Digital Power Supply PECL I/O Power Supply 3.3V Analog I/O and Power Supply DC logic signal input voltage DC logic signal input voltage DC logic signal output voltage Input current Input current
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -100 -100
6.0 6.0 6.0 VDDLVPECL +0.5 5.5 VDD3.3 +0.5 100 100
V V V V V V mA mA
NOTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods will severely affect device reliability.
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
VDD3.3 AVDD3.3 AVDD3.3 VDD
LVPECL
Power Supply Voltage Transmit Power Supply Voltage (AVDD3.3_TX) Receiver Power Supply Voltage (AVDD3.3_RX) PECL I/O Power Supply Voltage Total Power Supply Current Total Power Supply Current Total Power Consumption Total Power Consumption
3.135 3.135 3.135 3.135
3.3 3.3 3.3 3.3 200 242 660 800
3.465 3.465 3.465 3.465
V V V V mA mA mW mW
IDD-OC3 IDD-OC12 PDD-OC3 PDD-OC12
36
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER MIN TYP MAX UNITS CONDITIONS
VOH VOL VOCOMM VODIFF
LVPECL
Output High Voltage
VDDLVPECL - 0.9 0.7 1.1 VDDLVPECL - 1.3 1300
V
LVPECL LVPECL
Output Low Voltage Output Common Mode Voltage
V V
LVPECL
Output Differential Voltage
600
mV
Terminate with 50 to VDDLVPECL- 2.0 For Single-Ended For Single-Ended Peak-to-peak
VIH VIL VIDIFF VICOMM
LVPECL
Input High Voltage
VDDLVPECL - 0.9 0
VDDLVPECL - 0.3 VDDLVPECL - 1.72 1600 VDDLVPECL -1.0 -VIDIFF/2 VDD3.3 0.4 VDD3.3 0.8 50 500
V
LVPECL
Input Low Voltage
V
LVPECL LVPECL
Input PECL Differential Voltage Input PECL Common Mode Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current
400 1.5 - VIDIFF/2
mV V
VOH VOL VIH VIL IIH
LVTTL/ LVCMOS LVTTL/ LVCMOS LVTTL/ LVCMOS LVTTL/ LVCMOS LVTTL/ LVCMOS LVTTL/ LVCMOS
2.4 0 2.0 0
V V V V
A
IOH = -1.0mA IOL = 1.0mA
2.0VIIL
Input Low Current
-500
A
-0.5VNOTE: All input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible and LVTTL compliant to 1 mA maximum current drive.
37
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.2
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT91L31IQ
64-pin Plastic Quad Flat Pack (10.0 x 10.0 x 2.0 mm, QFP)
-40C to +85C
PACKAGE DIMENSIONS
XRT91L31
Note: The control dimension is in millimeters. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.072 0.096 1.82 2.45 A1 0.010 0.020 0.25 0.50 A2 0.071 0.087 1.80 2.20 B 0.007 0.011 0.17 0.27 C 0.004 0.009 0.11 0.23 D 0.510 0.530 12.95 13.45 D1 0.390 0.398 9.90 10.10 e 0.0197 BSC 0.50 BSC L 0.029 0.041 0.73 1.03 0 7 0 7
38
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REVISION HISTORY
REVISION # DATE DESCRIPTION
xr
REV. 1.0.2
1.0.0 1.0.1
October 2005 May 2006
XRT91L31 datasheet release version. 1.Added jitter performance results in Section 4.6. 2.Corrected RXDO[7:0] pin description to "update on falling edge". 3.Removed subscript on TXPCLK_IO in Table 10, Table 11, Table 12, & Table 13. 4.Revised standards compliance list on page 2. 5.Changed CAP1P, CAP2P, CAP1N, CAP2N pin description title. 6.Revised Section 4.5 and 4.6. 7.Removed TA = 25C test condition from electrical characteristics table. 8.Corrected CMUREFSEL in Figure 1 to CMUFREQSEL. 9.Revised LVPECL and LVTTL/LVCMOS DC electrical characteristics table. 10.Updated LVTTL input/output pin description to denote LVTTL/LVCMOS level.
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet Dec 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
39

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